The present invention generally relates to semiconductor devices and more particularly to a semiconductor device having a ball grid array and a fabrication process thereof, including a transportation tray used in the fabrication process of the semiconductor device. Further, the present invention relates to the fabrication process of a semiconductor substrate used for such a semiconductor device.
With ever-increasing demand of size reduction of electronic apparatuses, efforts are being made for decreasing the size and increasing the integration density of semiconductor devices. In relation to this, there is a proposal of a so-called chip-size package structure in which the overall size of the semiconductor device is made close to the size of the semiconductor chip therein.
In order to achieve such a real chip-size package structure, as well as for improving the efficiency of production of the semiconductor devices having such a package structure, there is a proposal of a wafer-level packaging process in which a substrate carrying a plurality of semiconductor devices thereon is subjected to a packaging process in the state that the semiconductor devices are still on the semiconductor substrate, followed by a dicing process to form individual semiconductor chips corresponding to the semiconductor devices.
FIG. 1 shows an example of a semiconductor device 10A fabricated according to a conventional wafer-level packaging process.
Referring to FIG. 1, the semiconductor device 10A generally includes a semiconductor chip 1A, a resin package layer 2 and a plurality of bump electrodes 3.
More specifically, the semiconductor device 10A carries the resin package layer 2 on the surface of the semiconductor chip 1A on which active devices (monolithic electronic circuits) and the bump electrodes 3 are formed. The substrate is then diced into individual semiconductor devices 10A. The semiconductor device 10A thus formed has a size substantially identical to the size of the semiconductor chip 1A.
FIG. 2 shows the construction of a conventional transportation tray 5 used for transporting the semiconductor device 10A of FIG. 1.
Referring to FIG. 2, the transportation tray 5 includes a tray main-body 6 accommodating therein the semiconductor device 10A, and a cap 7 is provided on the train main-body 6 so as to cover the opening of the tray main-body 6. The tray main-body 6 includes a bottom overhang part 8 wherein the bottom overhang part 8 supports the semiconductor device 10A by engaging the resin package layer 2 on the semiconductor chip 1A. The overhang part 8 defines an opening for accommodating the bump electrodes 3 in the state that the semiconductor device 10A is held inside the transportation tray 5.
FIG. 3 shows another conventional semiconductor device 10B fabricated according to a conventional wafer-level packaging process.
Referring to FIG. 3, the semiconductor device 10B generally includes, in addition to the semiconductor chip 1A described in FIG. 1, bump electrodes 4 formed on the semiconductor chip 1A and a circuit substrate 9 provided on the bump electrodes 4 in electrical as well as mechanical connection with the bump electrodes 4, wherein an under-fill resin layer 11 is formed so as to fill the gap between the semiconductor chip 1A and the circuit substrate 9. It should be noted that the bump electrodes 3 forming a ball grid array are formed on the bottom surface of the circuit substrate 9. By using the circuit substrate 9, which carries wiring patterns thereon, a dense array of the bump electrodes 3 becomes possible.
FIG. 4 shows a further conventional semiconductor device 10C fabricated according to a conventional wafer-level packaging process.
Referring to FIG. 4, the semiconductor device 10C has a construction generally identical with the construction of the semiconductor device 10B except that a thin semiconductor chip 1B is used. The semiconductor chip 1B having such a reduced thickness may be formed by grinding the rear surface of the semiconductor chip 1A.
FIGS. 5A-5D are diagrams showing an example of the fabrication process of a conventional semiconductor device.
In recent process of fabricating semiconductor devices, there is a tendency to increase the size of the semiconductor substrate so as to maximize the efficiency of production of the semiconductor devices. In order to obtain such a large-diameter semiconductor substrate, it is necessary to slice a large-diameter semiconductor crystal ingot by a wire saw machine and process the both surfaces of the large-diameter semiconductor wafer thus obtained.
FIG. 5A shows a semiconductor substrate 12A immediately after the sawing process. As can be seen in FIG. 5A, the both surfaces of the semiconductor substrate 12A form a rough surface, and thus, a smoothing process is essential in order that the semiconductor substrate 12A can be used for the substrate of a semiconductor device.
Thus, in the step of FIG. 5B, a hypothetical target surface state 13 is set for the semiconductor substrate 12A, and the rear surface (top surface in the example of FIG. 5B) of the semiconductor substrate 12A is processed in the step of FIG. 5C while using the top surface as a reference surface, such that the state of the rear surface reaches the target surface state 13. Further, the front surface (bottom surface in the example of FIG. 5B) is processed similarly in the step of FIG. 5D. The semiconductor devices 10A, 10B or 10C are formed on such a semiconductor substrate 12A in a row and column formation.
As noted already, the semiconductor device 10A has an advantageous feature in that the desired high-density mounting is possible on a circuit substrate of an electronic apparatus. On the other hand, it should be noted that the semiconductor device 10A has a composite structure 10 in which the semiconductor chip 1A carries a resin layer 2 on the side where the electrode bumps 3 are formed. As the resin layer 2 has a property substantially different from the property of the semiconductor chip 1A or the semiconductor substrate 12C, and in view of the fact that the semiconductor chip 1A, including the resin layer 2 thereon, has a rectangular shape defined by sharply defined edges and corners, there arises a problem, when sawing the semiconductor substrate 12C into the semiconductor chips 1A or when handling the semiconductor device, in that a crack may be formed at the boundary between the semiconductor substrate 12C and the resin layer 2. Alternatively, the semiconductor chip 1A or the resin layer 2 itself may be cracked. The same problem occurs not only in the semiconductor chip 1A but also in the semiconductor chip 1B or 1C.
Further, even in such a case in which the problem of cracking is avoided, the semiconductor device 10A, 10B or 10C is still vulnerable to damages particularly at the boundary between the semiconductor chip 1A and the resin layer 2, and a careful handling is needed in a suitable protective environment.
Further, the use of the transportation tray 5 of FIG. 2 in combination with the semiconductor device 10A, 10B or 10C may cause the problem of rattling of the semiconductor device 10A inside the tray main-body 6, while such a rattling is not only disadvantageous in view of poor reliability of transportation but also in view of unreliable contact with a test bed used when testing the semiconductor device 10A in the state that the semiconductor device 10A is held by the transportation tray 5. Further, the rattling of the semiconductor device 10A in the transportation tray 5 may cause a damage in the solder bumps 3 as a result of collision with the bottom overhang part 8 of the transportation tray 5.
In the case of the semiconductor device 10C in which the thickness of the semiconductor chip 1B is reduced, the semiconductor device is extremely fragile and handling of the substrate has to be conducted with an utmost care. This problem becomes particularly serious when a large size substrate is used for increasing the efficiency of production of the semiconductor devices.
Further, the process of forming the semiconductor substrate 12A shown in FIGS. 5A-5D has a drawback in that the substrate 12A tends to show an undulation formed at the time of sawing the semiconductor crystal ingot by a wire saw machine. Such an undulation is difficult to be removed by a mere grinding process conducted by using the surface 13 as a reference surface.
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device having a composite wafer-level packaging structure, wherein the problem of cracking of a resin layer covering a semiconductor chip or a crack formation at an interface between the resin layer and the semiconductor chip is successfully avoided.
Another object of the present invention is to provide a semiconductor chip having a top principal surface, said semiconductor chip carrying a plurality of bump electrodes on said top principal surface;
a resin layer covering said top principal surface of said semiconductor chip so as to seal said semiconductor chip,
said semiconductor chip and said resin layer thereby forming a composite semiconductor structure defined by a side wall having a plurality of corners, and
a chamfer surface formed in said side wall of said composite semiconductor structure as a part of said side wall such that said chamfer surface extends over said semiconductor chip and said resin layer.
Another object of the present invention is to provide a semiconductor device, comprising:
a semiconductor chip having a top principal surface, said semiconductor chip carrying a plurality of bump electrodes on said top principal surface;
a resin layer covering said top principal surface of said semiconductor chip so as to seal said semiconductor chip,
said semiconductor chip and said resin layer thereby forming a composite semiconductor structure defined by a side wall having a plurality of corners, and
a step surface formed in said resin layer along said side wall of said composite structure.
Another object of the present invention is to provide a semiconductor device, comprising:
a semiconductor chip having a top principal surface, said semiconductor chip carrying a plurality of bump electrodes on said top principal surface;
a resin layer covering said top principal surface of said semiconductor chip so as to seal said semiconductor chip,
a chamfer surface formed in a side wall of said semiconductor chip as a part of said side wall such that said chamfer surface surrounds said semiconductor chip along a top edge thereof,
said resin layer covering said chamfer surface.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming a resin layer on a principal surface of a semiconductor substrate;
grooving said resin layer along a dicing line on said semiconductor substrate to form a V-shaped groove having a substantially V-shaped cross-section such that said V-shaped groove reaches said semiconductor substrate; and
dicing, after said step of grooving, said semiconductor substrate along said V-shaped groove by forming a dicing groove with a width smaller than a width of said V-shaped groove.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming a resin layer on a principal surface of a semiconductor substrate;
dicing said semiconductor substrate along a dicing line by forming a dicing groove through said resin layer and through said semiconductor substrate; and
grooving, after said step of dicing of said semiconductor substrate, said resin layer along said dicing line to form a V-shaped groove having a substantially V-shaped cross-section in said resin layer such that said V-shaped groove has a width larger than a width of said dicing groove and reaches said semiconductor substrate.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming a resin layer on a principal surface of a semiconductor substrate;
grooving said resin layer along a dicing line on said semiconductor substrate to form a first groove having a substantially rectangular cross-section and a first width in said resin layer; and
dicing, after said step of grooving, said semiconductor substrate along said first groove by forming a second groove with a second width smaller than said first width of said first groove.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the step of:
adhering a semiconductor substrate on a dicing apparatus by an adhesive tape;
dicing said semiconductor substrate in a first direction such that said adhesive tape remains substantially intact;
dicing said semiconductor substrate in a second, different direction together with said adhesive tape, to form a plurality of adhesive strips each carrying thereon a plurality of semiconductor chips aligned in a row; and
applying a V-shaped saw blade having a V-shaped saw edge laterally to each of said adhesive strips such that said V-shaped saw blade cuts into a gap formed between a pair of adjacent semiconductor chips by said dicing step conducted in said first direction, said saw blade thereby forming a chamfer surface on a side wall of said semiconductor chips such that said chamfer surface extends, in each of said semiconductor chips, generally perpendicularly to a principal surface of said semiconductor chip.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
forming a V-shaped groove on a top surface of a semiconductor substrate, said semiconductor device carrying an electronic circuit on said top surface;
forming a resin layer on said top surface of said semiconductor substrate so as to fill said V-shaped groove; and
dicing said semiconductor substrate by a dicing saw having a blade width smaller than a width of said V-shaped groove, along said V-shaped groove.
According to the present invention, the composite semiconductor body forming the semiconductor device becomes substantially immune to damages caused by a shock or concentration of stress, as the composite semiconductor structure effectively dissipates the stress or shock applied thereto, particularly to the corner of the composite semiconductor structure.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
slicing a semiconductor substrate from a semiconductor ingot;
applying a resin layer on a first surface of said semiconductor substrate such that said resin layer has a planarized surface;
grinding a second surface of said semiconductor substrate while using said planarized surface of said resin layer as a reference surface, to form a planarized surface on said second surface; and
grinding said first surface while using said second, planarized surface as a reference surface, to form a planarized surface on said first surface.
According to the present invention, a semiconductor substrate having a smooth and flat surface suitable for construction of semiconductor devices thereon is obtained.
Another object of the present invention is to provide a transportation device of a semiconductor device, comprising:
a tray member adapted to support a semiconductor device in a face-down state, said semiconductor device carrying a plurality of bump electrodes thereon, said tray member having an opening for accommodating said bump electrodes when said semiconductor device is mounted on said tray member; and
a removable cap member provided on said tray member removably, said removable cap member covering said tray member in a state in which said semiconductor device is mounted on said tray member,
wherein said tray member includes a chamfer surface for engagement with a corresponding chamfer surface formed on said semiconductor device.
Another object of the present invention is to provide a transportation device of a semiconductor device, comprising:
a tray member adapted to support a semiconductor device in a face-down state, said semiconductor device carrying a plurality of bump electrodes thereon, said tray member having an opening for accommodating said bump electrodes when said semiconductor device is mounted on said tray member; and
a removable cap member provided on said tray member removably, said removable cap member covering said tray member in a state in which said semiconductor device is mounted on said tray member,
wherein said tray member includes a step surface for engagement with a corresponding step surface formed on said semiconductor device.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
mounting a semiconductor device having a chamfered surface and a plurality of bump electrodes on a transportation device,
said transportation device comprising a tray member adapted to support said semiconductor device in a face-down state, said tray member having an opening for accommodating said bump electrodes when said semiconductor device is mounted on said tray member, and a removable cap member provided on said tray member removably, said removable cap member covering said tray member in a state in which said semiconductor device is mounted on said tray member, said tray member including a chamfer surface for engagement with said chamfer surface on said semiconductor device; and
transporting said semiconductor device in a state mounted on said transportation device.
Another object of the present invention is to provide a method of fabricating a semiconductor device, comprising the steps of:
mounting a semiconductor device having a stepped surface and a plurality of bump electrodes on a transportation device,
said transportation device comprising a tray member adapted to support said semiconductor device in a face-down state, said tray member having an opening for accommodating said bump electrodes when said semiconductor device is mounted on said tray member, and a removable cap member provided on said tray member removably, said removable cap member covering said tray member in a state in which said semiconductor device is mounted on said tray member, said tray member including a stepped surface for engagement with said stepped surface on said semiconductor device; and
transporting said semiconductor device in a state mounted on said transportation device.
According to the present invention, the semiconductor device is positioned spontaneously to the desired nominal position inside the transportation tray with little rattling as a result of the engagement of the chamfered surfaces or the stepped surfaces. Thereby, the transportation of the semiconductor device is conducted reliably including the test process that is conducted while in the state the semiconductor device is held in the transportation tray.
Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attache drawings.